DC Line Model: CEEL2T

 

Model Equations and/or Block Diagrams

For a Detailed Treatment of how DC lines are implemented in the software see the help topic here.

Parameters:

ALFDY	minimum alpha for dynamics (degrees)
GAMDY	minimum gamma for dynamics (degrees)
DELAYVDCL	DELAY for VDCL (sec)
TIDR	current order time constant (sec)
SAMPLEVDCL	Sample rate for VDCL (sec)
VUNBL	rectifier ac unblocking voltage (pu)
TBLKBY	minimum blocking and bypass time (sec)
dVdI	Inverter DeltaV/DeltaI slope characteristic (V/amps)
VUNBY	inverter ac unbypassing voltage (pu)
ACCL	model acceleration factor
RSVOLT	minimum dc voltage following block (kV)
RSCUR	minimum dc current following block (amps)
VRAMP	voltage recovery rate (pu/sec)
CRAMP	current recovery rate (pu/sec)
C0	minimum current demand (amps)
CL	current lower on hysteresis limit (amps)
CH	current higher on hysteresis limit (amps) >= CL
VL1	voltage limit point 1 (pu)
VL2	voltage limit point 2 (pu)
VH1	voltage limit point 3 (pu)
VH2	voltage limit point 4 (pu)
ALFMXI	maximum inverter firing angle (degrees)
VDEBLK	rectifier ac voltage which causes a block if remains for time TDEBLK (pu)
TDEBLK	time delay for block (sec)
TREBLK	time delay after rectifier ac voltage recovers above VUNBL before line unblocks (sec)
VINBLK	inverter ac voltage which causes block after communication delay TCOMB (pu)
TCOMB	communication delay to signal rectifier to block because of low inverter voltage (sec)
VACBYP	inverter ac voltage which causes bypass if remains for time TDEBYP (pu)b
TDEBYP	time delay for bypass (sec)
TINBLK	time delay after inverter ac voltage recovers above VUNBY before line unblocks (this value should also include communication delay) (sec)
TINBYP	time delay after inverter ac voltage recovers above VUNBY before line unbypasses (sec)
TVP	power control VDC transducer time constant (sec)